1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device suitably used for diagnosing its internal logic circuit.
2. Description of the Related Art
With the increasing needs for high performance and high integration density of semiconductor integrated circuit devices, a great difficulty has been found in formation of test data required for determination of functions of internal logic circuits in manufactured semiconductor devices and for analysis of defective parts thereof. A scanning technique for internal logic circuit diagnosis of semiconductor integrated circuit devices is known as a promising technique for performing logic diagnostic tests with a small number of input/output terminal pins used in devices. According to this test technique, when a semiconductor device under test is failed and a logically abnormal operation is caused, in order to analyze its cause, the device is normally operated after the state of its internal logic circuit is externally and directly set, and then the state of the internal logic circuit after the operation is detected, thereby performing a logic diagnostic test.
According to such a conventional internal logic circuit diagnostic test technique, however, conflicting problems are posed, i.e., it is very difficult to effectively perform an internal logic diagnosis while minimizing the number of required input/output pins of a device. Especially, when an internal logic circuit arrangement of a semiconductor device under test is divided into several circuit units and only a desired circuit unit or units selected from these units are subjected to internal circuit diagnostic tests, input/output pins must be arranged, basically, in each circuit unit in order to meet this requirement. Otherwise, test efficiency or test speed is degraded. If all the circuit units are series-connected between the respective input and output pins, the number of pins in the device can be reliably minimized. However, a test process for designating a desired unit among all the circuit units becomes complicated and takes considerable time. On the contrary, if input/output pins are arranged in every circuit unit, a process of selecting or designating a desired circuit unit is simplified. In this case, however, the total number of input/output pins of the device is undesirably increased.